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## Search the dblp DataBase
Dale E. Hocevar:
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## Publications of Author- Richard Burch, Farid N. Najm, Ping Yang, Dale E. Hocevar
**Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits.**[Citation Graph (0, 0)][DBLP] DAC, 1988, pp:294-299 [Conf] - Dale E. Hocevar, Ching-Yu Hung, Dan Pickens, Sundararajan Sriram
**Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example.**[Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1998, pp:400-0 [Conf] - Dale E. Hocevar, Rajeev Arora, Uttiya Dasgupta, Sattam Dasgupta, Nagaraj Subramanyam, Sham Kashyap
**A Usable Circuit Optimizer for Designers.**[Citation Graph (0, 0)][DBLP] ICCAD, 1990, pp:290-293 [Conf] - Paul F. Cox, Richard Burch, Dale E. Hocevar, Ping Yang, Berton D. Epler
**Direct circuit simulation algorithms for parallel processing [VLSI].**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:6, pp:714-725 [Journal] - Paul F. Cox, Richard Burch, Ping Yang, Dale E. Hocevar
**New implicit integration method for efficient latency exploitation in circuit simulation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:10, pp:1051-1064 [Journal] - Joseph E. Hall, Dale E. Hocevar, Ping Yang, Michael J. McGraw
**SPIDER -- A CAD System for Modeling VLSI Metallization Patterns.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1023-1031 [Journal] - Dale E. Hocevar, Paul F. Cox, Ping Yang
**Parametric yield optimization for MOS circuit blocks.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:645-658 [Journal] - Dale E. Hocevar, Michael R. Lightner, Timothy N. Trick
**A Study of Variance Reduction Techniques for Estimating Circuit Yields.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:180-192 [Journal] - Dale E. Hocevar, Michael R. Lightner, Timothy N. Trick
**An Extrapolated Yield Approximation Technique for Use in Yield Maximization.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:4, pp:279-287 [Journal] - Dale E. Hocevar, Ping Yang, Timothy N. Trick, Berton D. Epler
**Transient Sensitivity Computation for MOSFET Circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:4, pp:609-620 [Journal] - Ping Yang, Dale E. Hocevar, Paul F. Cox, Charles F. Machala III, Pallab K. Chatterjee
**An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:5-14 [Journal] **A Reduced-Complexity, Scalable Implementation of Low Density Parity Check (LDPC) Decoder.**[Citation Graph (, )][DBLP]
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